The present invention generally relates to a method for forming a wafer level package and a device formed and more particularly, relates to a method for forming a wafer level package in which a plurality of solder balls are first formed on a plurality of bond pads before a layer of elastomeric material is formed on top of the wafer to encapsulate the plurality of solder balls with tip portions of the solder balls exposed for board level assembly and a device formed by the method.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become impractical for several reasons. One of the problems in utilizing solder paste screening technique in bonding modem semiconductor devices is the paste composition itself. A solder paste is formed by a flux material and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control as the solder bump volume decreases. Even though a solution of the problem has been proposed by using solder paste that contain extremely small and uniform solder particles, it can only be achieved at a high cost penalty. A second problem in utilizing the solder paste screening technique in modem high density semiconductor devices is the available space between solder bumps. It is known that a large volume reduction occurs when a solder changes from a paste state to a cured stated, the screen holes for the solder paste must be significantly larger in diameter than the actual solder bumps to be formed. The large volume shrinkage ratio thus makes the solder paste screening technique difficult to carry out in high density devices.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UMB layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UMB layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
A unique feature of the chip scale package is the use of an interposer layer that is formed of a flexible, compliant material. The interposer layer provides the capability of absorbing mechanical stresses during the package forming steps and furthermore, allows thermal expansion mismatch between the die and the substrate. The interposer layer, therefore, acts both as a stress buffer and as a thermal expansion buffer. Another unique feature of the chip scale package, i.e., such as a micro-BGA package, is its ability to be assembled to a circuit board by using conventional surface mount technology (SMT) processes.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 xcexcm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 xcexcm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches.
To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
It is therefore an object of the present invention to provide a method for forming a wafer level package for fabricating IC devices that does not have the drawbacks or the shortcomings of the conventional IC device fabrication techniques.
It is another object of the present invention to provide a method for forming a wafer level package that combines the benefits of chip scale packaging and low cost whole wafer packaging.
It is a further object of the present invention to provide a method for forming a wafer level package by first forming a plurality of solder balls on bond pads and then encapsulating the plurality of solder balls in a layer of compliant material.
It is another further object of the present invention to provide a method for forming a wafer level package by first forming a plurality of solder balls on bond pads and then coating a layer of elastomeric material on top of the wafer substantially encapsulating the plurality of solder balls.
It is still another object of the present invention to provide a method for forming a wafer level package by encapsulating a plurality of solder balls formed on a wafer surface and then thermally annealing an elastomeric material to improve its stress buffering characteristics.
It is yet another object of the present invention to provide a method for forming a wafer level package by first forming a plurality of solder balls encapsulated in an elastomeric layer and then etching the layer such that tip portions of the solder balls are substantially exposed for subsequent bonding in a board level assembly.
It is still another further object of the present invention to provide a wafer level package that has solder balls formed on top encapsulated in a layer of flexible, compliant material such as an elastomer as a buffering layer for mechanical stresses and thermal expansion mismatches.
It is yet another further object of the present invention to provide a wafer level package for low cost fabrication wherein solder balls and a stress buffering layer are sequentially formed on a wafer surface prior to the severing of individual IC dies from the wafer.
In accordance with the present invention, a method for forming a wafer level package and IC devices formed by the method are disclosed.
In a preferred embodiment, a method for forming a wafer level package can be carried out by first providing a pre-processed semi-conducting wafer that has a first plurality of bond pads formed on top and insulated by a passivation layer, depositing an electrically conductive layer on top of the wafer, defining and forming conductive lines in the conductive layer, forming a dielectric layer on top of the conductive lines, defining a second plurality of bond pads in the dielectric layer over the conductive lines, planting solder balls on the second plurality of bond pads, forming an elastic material layer on top of the wafer, and exposing tip portions of the solder balls by an etching step.
The method for forming a wafer level package may further include the step of increasing a height of the solder balls by a secondary solder ball planting process. The first plurality of bond pads may be situated along a peripheral edge of the IC dies on the wafer. The electrically conductive layer deposited on top of the wafer may be a metallic layer which has a thickness between about 2 xcexcm and about 10 xcexcm. The metallic layer may be formed of a metal selected from the group consisting of aluminum, copper, aluminum alloys and copper alloys. The conductive lines formed from the conductive layer may first be defined by a photolithographic process, and then formed by an etching process. The conductive lines may be formed as metal traces for extending the first plurality of bond pads located at a peripheral edge of the IC die to a central region of the die. The conductive lines may further be formed as metal traces for connecting the first plurality of bond pads into an area array on the surface of the IC dies.
In the method for forming a wafer level package, the dielectric material layer may be deposited by a technique selected from the group consisting of coating, printing and laminating. The dielectric material layer may be deposited to a thicknesses of between about 2 xcexcm and about 20 xcexcm. The dielectric material layer may be deposited of a material selected from the group consisting of polyimide, BCB (Benzocyclobutene) and other suitable polymeric materials. The second plurality of bond pads may be input/output pads that are defined by a photolithographic method. The method may further include the step of forming ball limiting metallurgy layers on the second plurality of bond pads prior to the planting of solder balls.
The method for forming a wafer level package may further include the step of depositing a ball limiting metallurgy layer on top of the wafer, and then defining the ball limiting metallurgy layer such that it only covers the second plurality of bond pads prior to the planting of the solder balls. The solder balls may be planted on the second plurality of bond pads by a technique selected from the group consisting of screen printing, electrodeposition, electroless deposition and stencil printing. The elastic material layer may be formed on top of the wafer to a thickness between about 50 xcexcm and about 200 xcexcm. The elastic material may be formed by a method of printing or coating. The elastic material may be an elastomer that includes silicone rubber. The method may further include the step of thermally annealing the elastic material layer until tip portions of the solder balls are exposed from the elastic material layer. The etching step for exposing tip portions of the solder may be carried out by a dry etching or a wet etching process.
In an alternate embodiment, the present invention method for forming a wafer level package with solder balls on top may be carried out by the operating steps of providing a pre-processed silicon wafer which has a first plurality of bond pads on top situated in a passivation layer, depositing a metal layer to a thickness of between about 2 xcexcm and about 10 xcexcm on top of the silicon wafer, defining metal traces in the metal layer by a photolithographic method, forming metal traces from the metal layer in an etching process, depositing a dielectric layer which has a thickness between about 2 xcexcm and about 20 xcexcm on top of the metal traces, defining a second plurality of bond pads in the dielectric layer over the metal traces by a photolithographic method, forming the second plurality of bond pads in an etching step over the metal traces, depositing a ball limiting metallurgy layer on top of the second plurality of bond pads, planting solder balls on the ball limiting metallurgy layer and the second plurality of bond pads by a technique selected from the group consisting of screen printing, electrodeposition, electroless deposition and stencil printing, depositing an elastomeric layer which has a thickness between about 50 xcexcm and about 200 xcexcm on top of the wafer surface, annealing under heat the elastomeric layer such that tip portions of the solder balls are exposed from the elastomeric layer, and exposing substantially tip portions of the solder balls by an etching step. The method may further include the step of increasing a height of the solder balls by a secondary solder balls planting process.
The present invention is further directed to a wafer level package which has solder balls formed on top that includes a pre-processed silicon wafer that has a first plurality of bond pads formed on top, the first plurality of bond pads are insulated by a passivation layer, a plurality of metal traces formed on top of the wafer providing electrical communication with the first plurality of bond pads, a dielectric layer deposited on top of the metal traces, a second plurality of bond pads formed in the dielectric layer over the metal traces in electrical communication with the first plurality of bond pads, a second plurality of solder balls formed on the second plurality of bond pads, and an elastomeric material substantially encapsulating the second plurality of solder balls with tip portions of the solder balls exposed for subsequent board level assembly.
In the wafer level package which has solder balls formed on top and encapsulated in a flexible layer, the elastomer layer may be formed of an elastomeric material that has an elasticity sufficient to buffer stresses imposed on the wafer during the solder ball forming process. The elastomeric material layer may be formed of an elastomer that includes silicone rubber and fluorosillicone rubber. The solder balls may have improved height by the planting of secondary solder balls on top. The metal traces may be formed of a metal of aluminum, copper, aluminum alloys or copper alloys. The dielectric layer may be deposited of polyimide or BCB.